Datasheet

49.5.5 Interrupts
The interrupt request line is connected to the Interrupt Controller. In order to use interrupt requests of this
peripheral, the Interrupt Controller (NVIC) must be configured first. Refer to Nested Vector Interrupt
Controller for details.
Related Links
10.2 Nested Vector Interrupt Controller
49.5.6 Events
The events of this peripheral are connected to the Event System.
Related Links
31. EVSYS – Event System
49.5.7 Debug Operation
When the CPU is halted in Debug mode, this peripheral will halt normal operation. This peripheral can be
forced to continue operation during debugging - refer to the Debug Control (DBGCTRL) register for
details.
Refer to 49.8.8 DBGCTRL register for details.
49.5.8 Register Access Protection
Registers with write access can be optionally write-protected by the Peripheral Access Controller (PAC),
except for the following:
• Interrupt Flag register (INTFLAG)
• Status register (STATUS)
• Period and Period Buffer registers (PER, PERBUF)
• Compare/Capture and Compare/Capture Buffer registers (CCx, CCBUFx)
• Control Waveform register (WAVE)
• Pattern Generation Value and Pattern Generation Value Buffer registers (PATT, PATTBUF)
Note: Optional write protection is indicated by the "PAC Write Protection" property in the register
description.
Write protection does not apply for accesses through an external debugger.
49.5.9 Analog Connections
Not applicable.
49.6 Functional Description
49.6.1 Principle of Operation
The following definitions are used throughout the documentation:
SAM D5x/E5x Family Data Sheet
TCC – Timer/Counter for Control Applications
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1802