Datasheet

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Pin Name Type Description
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TCC/WO[WO_NUM-1] Digital output Compare channel n waveform output
Refer to I/O Multiplexing and Considerations for details on the pin mapping for this peripheral. One signal
can be mapped on several pins.
Related Links
6. I/O Multiplexing and Considerations
49.5 Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
49.5.1 I/O Lines
In order to use the I/O lines of this peripheral, the I/O pins must be configured using the I/O Pin Controller
(PORT).
Related Links
32. PORT - I/O Pin Controller
49.5.2 Power Management
This peripheral can continue to operate in any Sleep mode where its source clock is running. The
interrupts can wake up the device from Sleep modes. Events connected to the event system can trigger
other operations in the system without exiting Sleep modes.
49.5.3 Clocks
The TCC bus clocks (CLK_TCCx_APB) can be enabled and disabled in the Main Clock module. The
default state of CLK_TCCx_APB can be found in the Peripheral Clock Masking section (see the Related
Links below).
A generic clock (GCLK_TCCx) is required to clock the TCC. This clock must be configured and enabled
in the generic clock controller before using the TCC.
The generic clocks (GCLK_TCCx) are asynchronous to the bus clock (CLK_TCCx_APB). Due to this
asynchronicity, writing certain registers will require synchronization between the clock domains. Refer to
49.6.7 Synchronization for further details.
Related Links
15.6.2.6 Peripheral Clock Masking
14. GCLK - Generic Clock Controller
49.5.4 DMA
The DMA request lines are connected to the DMA Controller (DMAC). In order to use DMA requests with
this peripheral the DMAC must be configured first. Refer to DMAC – Direct Memory Access Controller for
details.
Related Links
22. DMAC – Direct Memory Access Controller
SAM D5x/E5x Family Data Sheet
TCC – Timer/Counter for Control Applications
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1801