Datasheet

48.7.3.12 Synchronization Busy
Name: SYNCBUSY
Offset: 0x10
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
CC1 CC0 COUNT STATUS CTRLB ENABLE SWRST
Access
R R R R R R R
Reset 0 0 0 0 0 0 0
Bits 6, 7 – CCx Compare/Capture Channel x Synchronization Busy
For details on CC channels number, refer to each TC feature list.
This bit is set when the synchronization of CCx between clock domains is started.
This bit is also set when the CCBUFx is written, and cleared on update condition. The bit is automatically
cleared when the STATUS.CCBUFx bit is cleared.
Bit 4 – COUNT COUNT Synchronization Busy
This bit is cleared when the synchronization of COUNT between the clock domains is complete.
This bit is set when the synchronization of COUNT between clock domains is started.
Bit 3 – STATUS STATUS Synchronization Busy
This bit is cleared when the synchronization of STATUS between the clock domains is complete.
This bit is set when a '1' is written to the Capture Channel Buffer Valid status flags (STATUS.CCBUFVx)
and the synchronization of STATUS between clock domains is started.
Bit 2 – CTRLB CTRLB Synchronization Busy
This bit is cleared when the synchronization of CTRLB between the clock domains is complete.
This bit is set when the synchronization of CTRLB between clock domains is started.
Bit 1 – ENABLE ENABLE Synchronization Busy
This bit is cleared when the synchronization of ENABLE bit between the clock domains is complete.
This bit is set when the synchronization of ENABLE bit between clock domains is started.
SAM D5x/E5x Family Data Sheet
TC – Timer/Counter
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1794