Datasheet

Table Of Contents

48.7.3.8 Status

Name: STATUS

Offset: 0x0B

Reset: 0x01

Property: Read-Synchronized

Bit 7 6 5 4 3 2 1 0

CCBUFV1 CCBUFV0 PERBUFV SLAVE STOP

Access

R/W R/W R/W R R

Reset 0 0 0 0 1

Bits 4, 5 – CCBUFV Channel x Compare or Capture Buffer Valid

For a compare channel x, the bit x is set when a new value is written to the corresponding CCBUFx

The bit x is cleared by writing a '1' to it when CTRLB.LUPD is set, or it is cleared automatically by

hardware on UPDATE condition.

For a capture channel x, the bit x is set when a valid capture value is stored in the CCBUFx register. The

bit x is cleared automatically when the CCx register is read.

Bit 3 – PERBUFV Period Buffer Valid

This bit is set when a new value is written to the PERBUF register. The bit is cleared by writing '1' to the

corresponding location when CTRLB.LUPD is set, or automatically cleared by hardware on UPDATE

condition. This bit is available only in 8-bit mode and will always read zero in 16- and 32-bit modes.

Bit 1 – SLAVE Slave Status Flag

This bit is only available in 32-bit mode on the slave TC (i.e., TC1 and/or TC3). The bit is set when the

associated master TC (TC0 and TC2, respectively) is set to run in 32-bit mode.

Bit 0 – STOP Stop Status Flag

This bit is set when the TC is disabled, on a Stop command, or on an overflow/underflow condition when

the One-Shot bit in the Control B Set register (CTRLBSET.ONESHOT) is '1'.

Value Description

Counter is running.

Counter is stopped.

SAM D5x/E5x Family Data Sheet

TC – Timer/Counter

Datasheet

DS60001507E-page 1790