Datasheet

individually by writing a '1' to the corresponding enabling bit in the Interrupt Enable Set (INTENSET)
register, and disabled by writing a '1' to the corresponding clearing bit in the Interrupt Enable Clear
(INTENCLR) register.
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled.
The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the
peripheral is reset. An interrupt flag is cleared by writing a '1' to the corresponding bit in the INTFLAG
register. Each peripheral can have one interrupt request line per interrupt source or one common interrupt
request line for all the interrupt sources.If the peripheral has one common interrupt request line for all the
interrupt sources, the user must read the INTFLAG register to determine which interrupt condition is
present.
Related Links
18. PM – Power Manager
10.2.1 Overview
15.6.5 Events
Not applicable.
15.6.6 Sleep Mode Operation
In IDLE sleep mode, the MCLK is still running on the selected main clock.
In STANDBY sleep mode, the MCLK is frozen if no synchronous clock is required.
SAM D5x/E5x Family Data Sheet
MCLK – Main Clock
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Datasheet
DS60001507E-page 177