Datasheet

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CPU Clock Domain
Peripheral Clock Default State
CLK_USB_AHB Enabled
CLK_USB_APB Disabled
CLK_WDT_APB Enabled
CLK_DAC_APB Disabled
CLK_DSU_APB Enabled
CLK_CCL_APB Disabled
CLK_QSPI_APB Enabled
CLK_ICM_APB Disabled
CLK_TRNG_APB Disabled
Backup Clock Domain
Peripheral Clock Default State
CLK_OSC32KCTRL_APB Enabled
CLK_PM_APB Enabled
CLK_SUPC_APB Enabled
CLK_RSTC_APB Enabled
CLK_RTC_APB Enabled
When the APB clock is not provided to a module, its registers cannot be read or written. The module can
be re-enabled later by writing the corresponding mask bit to '1'.
A module may be connected to several clock domains (for instance, AHB and APB), in which case it will
have several mask bits.
Note that clocks should only be switched off if it is certain that the module will not be used: Switching off
the clock for the NVM Controller (NVMCTRL) will cause a problem if the CPU needs to read from the
Flash Memory. Switching off the clock to the MCLK module (which contains the mask registers) or the
corresponding APBx bridge, will make it impossible to write the mask registers again. In this case, they
can only be re-enabled by a system reset.
15.6.3 DMA Operation
Not applicable.
15.6.4 Interrupts
The peripheral has the following interrupt sources:
• Clock Ready (CKRDY): indicates that CPU clocks are ready. This interrupt is a synchronous wake-up
source.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status
and Clear (INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be enabled
SAM D5x/E5x Family Data Sheet
MCLK – Main Clock
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 176