Datasheet

Value Description
0
The TC is halted in standby.
1
The TC continues to run in standby.
Bits 5:4 – PRESCSYNC[1:0] Prescaler and Counter Synchronization
These bits select whether the counter should wrap around on the next GCLK_TCx clock or the next
prescaled GCLK_TCx clock. It also makes it possible to reset the prescaler.
These bits are not synchronized.
Value Name Description
0x0
GCLK Reload or reset the counter on next generic clock
0x1
PRESC Reload or reset the counter on next prescaler clock
0x2
RESYNC Reload or reset the counter on next generic clock. Reset the prescaler counter
0x3
- Reserved
Bits 3:2 – MODE[1:0] Timer Counter Mode
These bits select the counter mode.
These bits are not synchronized.
Value Name Description
0x0
COUNT16 Counter in 16-bit mode
0x1
COUNT8 Counter in 8-bit mode
0x2
COUNT32 Counter in 32-bit mode
0x3
- Reserved
Bit 1 – ENABLE Enable
Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/
disabled. The value written to CTRLA.ENABLE will read back immediately, and the ENABLE
Synchronization Busy bit in the SYNCBUSY register (SYNCBUSY.ENABLE) will be set.
SYNCBUSY.ENABLE will be cleared when the operation is complete.
This bit is not enable protected.
Value Description
0
The peripheral is disabled.
1
The peripheral is enabled.
Bit 0 – SWRST Software Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets all registers in the TC, except DBGCTRL, to their initial state, and the TC will
be disabled.
Writing a '1' to CTRLA.SWRST will always take precedence; all other writes in the same write-operation
will be discarded.
SAM D5x/E5x Family Data Sheet
TC – Timer/Counter
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1757