Datasheet

15.6.2.4 Selecting the Synchronous Clock Division Ratio
The main clock GCLK_MAIN feeds an 8-bit prescaler, which can be used to generate the synchronous
clocks. By default, the synchronous clocks run on the undivided main clock. The user can select a
prescaler division for the CPU clock domain by writing the Division (DIV) bits in the CPU Clock Division
register CPUDIV, resulting in a CPU clock domain frequency determined by this equation:


=



Frequencies must never exceed the specified maximum frequency for each clock domain given in the
electrical characteristics specifications.
If the application attempts to write forbidden values in CPUDIV register, register is written but these bad
values are not used and a violation is reported to the PAC module.
Division bits (DIV) can be written without halting or disabling peripheral modules. Writing DIV bits allows a
new clock setting to be written to all synchronous clocks belonging to the corresponding clock domain at
the same time.
Figure 15-2. Synchronous Clock Selection and Prescaler
Prescaler
Sleep Controller
Sleep mode
HSDIV
CPUDIV
CLK_CPU
GCLK
GCLK_MAIN
Clock
gate
Clock gate
Clock gate
CLK_AHB_CPU
clk_ahb_ip0
clk_ahb_ip1
clk_ahb_ipn
Clock
gate
Clock
gate
CLK_APB_CPU
clk_apb_ip0
clk_apb_ip1
clk_apb_ipn
Clock
gate
Clock
gate
PERIPHERALS
CPU
Clock gate
Clock gate
CLK_APB_HS
clk_apb_ip0
clk_apb_ip1
clk_apb_ipn
Clock
gate
Clock
gate
MASK
PERIPHERALS
HS
Clock Domain: f
HS
CPU
Clock Domain: fCPU
MASK
MASK
Note: A FAST clock for QSPI (CLK_QSPI2X_AHB) is derived from high-speed synchronous f
HS
.
Related Links
27. PAC - Peripheral Access Controller
15.6.2.5 Clock Ready Flag
There is a slight delay between writing to CPUDIV until the new clock settings become effective.
During this interval, the Clock Ready flag in the Interrupt Flag Status and Clear register
(INTFLAG.CKRDY) will return zero when read. If CKRDY in the INTENSET register is set to '1', the Clock
Ready interrupt will be triggered when the new clock setting is effective. The clock settings (CLKCFG)
must not be re-written while INTFLAG. CKRDY reads '0'. The system may become unstable or hang, and
a violation is reported to the PAC module.
SAM D5x/E5x Family Data Sheet
MCLK – Main Clock
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 173