Datasheet

Table Of Contents

Figure 48-16. Maximum Capture Operation with CC0 Initialized with ZERO Value

COUNT

"match"

ZERO

"clear" update

Input event

TOP

CC0

CC0 Event/

Interrupt

48.6.4 DMA Operation

The TC can generate the following DMA requests:

• Overflow (OVF): the request is set when an update condition (overflow, underflow or re-trigger) is

detected, the request is cleared by hardware on DMA acknowledge.

• Match or Capture Channel x (MCx): for a compare channel, the request is set on each compare

match detection, the request is cleared by hardware on DMA acknowledge. For a capture channel,

the request is set when valid data is present in the CCx register, and cleared when CCx register is

read.

48.6.5 Interrupts

The TC has the following interrupt sources:

• Overflow/Underflow (OVF)

• Match or Capture Channel x (MCx)

• Capture Overflow Error (ERR)

Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status

and Clear register (INTFLAG) is set when the interrupt condition occurs.

Each interrupt can be individually enabled by writing a '1' to the corresponding bit in the Interrupt Enable

Set register (INTENSET), and disabled by writing a '1' to the corresponding bit in the Interrupt Enable

Clear register (INTENCLR).

An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled.

The interrupt request remains active until either the interrupt flag is cleared, the interrupt is disabled, or

the TC is reset. See INTFLAG for details on how to clear interrupt flags.

The TC has one common interrupt request line for all the interrupt sources. The user must read the

INTFLAG register to determine which interrupt condition is present.

Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to Nested

Vector Interrupt Controller for details.