Datasheet

Figure 48-9. Unbuffered Single-Slope Down-Counting Operation
COUNT
MAX
New TOP written to
PER that is higher
than current COUNT
New TOP written to
PER that is lower
than current COUNT
"reload" update
"write"
ZERO
When double buffering is used, the buffer can be written at any time and the counter will still maintain
correct operation. The period register is always updated on the update condition, as shown in Figure
48-10. This prevents wraparound and the generation of odd waveforms.
Figure 48-10. Changing the Period Using Buffering
COUNT
MAX
New TOP written to
PER that is higher
than current COUNT
" clear" update
" write"
ZERO
New TOP written to
PER that is lower
than current COUNT
48.6.2.8 Capture Operations
To enable and use capture operations, the corresponding Capture Channel x Enable bit in the Control A
register (CTRLA.CAPTENx) must be written to '1'.
A capture trigger can be provided by input event line TC_EV or by asynchronous IO pin WO[x] for each
capture channel or by a TC event. To enable the capture from input event line, Event Input Enable bit in
the Event Control register (EVCTRL.TCEI) must be written to '1'. To enable the capture from the IO pin,
the Capture On Pin x Enable bit in CTRLA register (CTRLA.COPENx) must be written to '1'.
Note:
1. The RETRIGGER, COUNT and START event actions are available only on an event from the Event
System.
2. Event system channels must be configured to operate in asynchronous mode of operation when
used for capture operations.
By default, a capture operation is done when a rising edge is detected on the input signal. Capture on
falling edge is available, its activation is depending on the input source:
• When the channel is used with a IO pin, write a '1' to the corresponding Invert Enable bit in the Drive
Control register (DRVCTRL.INVENx).
SAM D5x/E5x Family Data Sheet
TC – Timer/Counter
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1722