Datasheet

Figure 48-7. Compare Channel Double Buffering
CCBUFVx
UPDATE
"write enable"
"data write"
=
COUNT
"match"
EN
EN
CCBUFx
CCx
Both the registers (PER/CCx) and corresponding buffer registers (PERBUF/CCBUFx) are available in the
I/O register map, and the double buffering feature is not mandatory. The double buffering is disabled by
writing a '1' to CTRLBSET.LUPD.
Note: In NFRQ, MFRQ or PWM down-counting counter mode (CTRLBSET.DIR=1), when double
buffering is enabled (CTRLBCLR.LUPD=1), PERBUF register is continously copied into the PER
independently of update conditions.
Changing the Period
The counter period can be changed by writing a new TOP value to the Period register (PER or CC0,
depending on the waveform generation mode), which is available in 8-bit mode. Any period update on
registers (PER or CCx) is effective after the synchronization delay.
Figure 48-8. Unbuffered Single-Slope Up-Counting Operation
COUNT
MAX
New TOP written to
PER that is higher
than current COUNT
Counter Wraparound
New TOP written to
PER that is lower
than current COUNT
"clear" update
"write"
ZERO
A counter wraparound can occur in any operation mode when up-counting without buffering, see Figure
48-8.
COUNT and TOP are continuously compared, so when a new TOP value that is lower than current
COUNT is written to TOP, COUNT will wrap before a compare match.
SAM D5x/E5x Family Data Sheet
TC – Timer/Counter
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1721