Datasheet

Table Of Contents

15.5.7 Debug Operation

When the CPU is halted in debug mode, the MCLK continues normal operation. In sleep mode, the

clocks generated from the MCLK are kept running to allow the debugger accessing any module. As a

consequence, power measurements are incorrect in debug mode.

15.5.8 Register Access Protection

All registers with write access can be write-protected optionally by the Peripheral Access Controller

(PAC), except for the following registers:

• Interrupt Flag register (INTFLAG)

Optional write protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write

Protection" property in each individual register description.

PAC write protection does not apply to accesses through an external debugger.

Related Links

27. PAC - Peripheral Access Controller

15.5.9 Analog Connections

Not applicable.

15.6 Functional Description

15.6.1 Principle of Operation

The CLK_MAIN clock signal from the GCLK module is the source for the main clock, which in turn is the

common root for the synchronous clocks for the CPU, APBx, and AHBx modules. The CLK_MAIN is

divided by an 8-bit prescaler. Each of the derived clocks can run from any divided or undivided main

clock, ensuring synchronous clock sources for each clock domain. The clock domain (CPU) can be

changed on the fly to respond to variable load in the application. The clocks for each module in a clock

domain can be masked individually to avoid power consumption in inactive modules. Depending on the

sleep mode, some clock domains can be turned off.

15.6.2 Basic Operation

15.6.2.1 Initialization

After a Reset, the default clock source of the CLK_MAIN clock (GCLK_MAIN) is started and calibrated

before the CPU starts running. The GCLK_MAIN clock is selected as the main clock without any

prescaler division.

By default, only the necessary clocks are enabled.

15.6.2.2 Enabling, Disabling, and Resetting

The MCLK module is always enabled and cannot be reset.

15.6.2.3 Selecting the Main Clock Source

Refer to the Generic Clock Controller description for details on how to configure the clock source of the

GCLK_MAIN clock.