Datasheet

Prescaler outputs from 1 to 1/1024 are available. For a complete list of available prescaler outputs, see
the register description for the Prescaler bit group in the Control A register (CTRLA.PRESCALER).
Note: When counting events, the prescaler is bypassed.
The joint stream of prescaler ticks and event action ticks is called CLK_TC_CNT.
Figure 48-2. Prescaler
PRESCALER
GCLK_TC /
{1,2,4,8,64,256,1024}
GCLK_TC
Prescaler
COUNT
CLK_TC_CNT
EVACT
EVENT
48.6.2.4 Counter Mode
The counter mode is selected by the Mode bit group in the Control A register (CTRLA.MODE). By default,
the counter is enabled in the 16-bit counter resolution. Three counter resolutions are available:
• COUNT8: The 8-bit TC has its own Period Value and Period Buffer Value registers (PER and
PERBUF).
• COUNT16: 16-bit is the default counter mode. There is no dedicated period register in this mode.
• COUNT32: 32-bit mode is achieved by pairing two 16-bit TC peripherals. TC(2n) is paired with TC(2n
+1).
When paired, the TC peripherals are configured using the registers of the even-numbered TC. The
TC bus clocks (CLK_TCx_APB) for both master and slave TCs need to be enabled.
The odd-numbered partner will act as a slave, and the Slave bit in the Status register
(STATUS.SLAVE) will be set. The register values of a slave will not reflect the registers of the 32-bit
counter. Writing to any of the slave registers will not affect the 32-bit counter. Normal access to the
slave COUNT and CCx registers is not allowed.
48.6.2.5 Counter Operations
Depending on the mode of operation, the counter is cleared, reloaded, incremented, or decremented at
each TC clock input (CLK_TC_CNT). A counter clear or reload marks the end of the current counter cycle
and the start of a new one.
The counting direction is set by the Direction bit in the Control B register (CTRLB.DIR). If this bit is zero
the counter is counting up, and counting down if CTRLB.DIR=1. The counter will count up or down for
each tick (clock or event) until it reaches TOP or ZERO. When it is counting up and TOP is reached, the
counter will be set to zero at the next tick (overflow) and the Overflow Interrupt Flag in the Interrupt Flag
Status and Clear register (INTFLAG.OVF) will be set. When it is counting down, the counter is reloaded
with the TOP value when ZERO is reached (underflow), and INTFLAG.OVF is set.
INTFLAG.OVF can be used to trigger an interrupt, a DMA request, or an event. An overflow/underflow
occurrence (i.e., a compare match with TOP/ZERO) will stop counting if the One-Shot bit in the Control B
register is set (CTRLBSET.ONESHOT).
It is possible to change the counter value (by writing directly in the COUNT register) even when the
counter is running. When starting the TC, the COUNT value will be either ZERO or TOP (depending on
the counting direction set by CTRLBSET.DIR or CTRLBCLR.DIR), unless a different value has been
written to it, or the TC has been stopped at a value other than ZERO. The write access has higher priority
than count, clear, or reload. The direction of the counter can also be changed when the counter is
running. See also the following figure.
SAM D5x/E5x Family Data Sheet
TC – Timer/Counter
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1716