Datasheet

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6. I/O Multiplexing and Considerations
48.5 Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
48.5.1 I/O Lines
In order to use the I/O lines of this peripheral, the I/O pins must be configured using the I/O Pin Controller
(PORT).
Table 48-2. I/O Lines
Instance Signal I/O Line Peripheral Function
MODULE0 SIGNAL PAxx A
Related Links
32. PORT - I/O Pin Controller
48.5.2 Power Management
This peripheral can continue to operate in any Sleep mode where its source clock is running. The
interrupts can wake up the device from Sleep modes. Events connected to the event system can trigger
other operations in the system without exiting Sleep modes.
Related Links
18. PM – Power Manager
48.5.3 Clocks
The TC bus clocks (CLK_TCx_APB) can be enabled and disabled in the Main Clock Module. The default
state of CLK_TCx_APB can be found in the Peripheral Clock Masking.
The generic clocks (GCLK_TCx) are asynchronous to the user interface clock (CLK_TCx_APB). Due to
this asynchronicity, accessing certain registers will require synchronization between the clock domains.
Refer to Synchronization for further details.
Note: Two instances of the TC may share a peripheral clock channel. In this case, they cannot be set to
different clock frequencies. Refer to the peripheral clock channel mapping of the Generic Clock Controller
(GCLK.PCHTRLm) to identify shared peripheral clocks.
Related Links
14.8.4 PCHCTRLm
15.6.2.6 Peripheral Clock Masking
48.5.4 DMA
The DMA request lines are connected to the DMA Controller (DMAC). In order to use DMA requests with
this peripheral the DMAC must be configured first. Refer to DMAC – Direct Memory Access Controller for
details.
Related Links
22. DMAC – Direct Memory Access Controller
SAM D5x/E5x Family Data Sheet
TC – Timer/Counter
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1712