Datasheet

47.8.9 DAC0 Control
Name: DACCTRL0
Offset: 0x0C
Reset: 0x0000
Property: PAC Write-Protection, Enabled-Protected
Bit 15 14 13 12 11 10 9 8
OSR[2:0] REFRESH[3:0]
Access
R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
DITHER RUNSTDBY FEXT CCTRL[1:0] ENABLE LEFTADJ
Access
R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Bits 15:13 – OSR[2:0] Oversampling Ratio
This field defines the oversampling ratio/interpolation depth.
Value Name Description
0x0
OSR_1 1x OSR (no interpolation)
0x1
OSR_2 2x OSR
0x2
OSR_4 4x OSR
0x3
OSR_8 8x OSR
0x4
OSR_16 16x OSR
0x5
OSR_32 32x OSR
other
- Reserved
Bits 11:8 – REFRESH[3:0] Refresh period
This field defines the refresh period. If REFRESH=0x0, the refresh mode is disabled. If REFRESH>0x1,
else the refresh period is:

REFRESH
= REFRESH × 30μs
Bit 7 – DITHER Dithering Mode
Value Description
0
Dithering mode is disabled.
1
Dithering mode is enabled.
Bit 6 – RUNSTDBY Run in Standby
This bit controls the behavior of DAC0 during standby sleep mode.
Value Description
0
DAC0 is disabled during standby sleep mode.
1
DAC0 continues to operate during standby sleep mode.
Bit 5 – FEXT External Filter Enable
This bit controls the usage of the filter.
Value Description
0
The filter is integrated to the DAC
SAM D5x/E5x Family Data Sheet
DAC – Digital-to-Analog Converter
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1699