Datasheet

47.8.8 Synchronization Busy
Name: SYNCBUSY
Offset: 0x08
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
DATABUF1 DATABUF0 DATA1 DATA0 ENABLE SWRST
Access
R R R R R R
Reset 0 0 0 0 0 0
Bit 5 – DATABUF1 Data Buffer DAC1
This bit is set when DATABUF1 register is written.
This bit is cleared when DATABUF1 synchronization is completed.
Value Description
0
No ongoing synchronized access.
1
Synchronized access is ongoing.
Bit 4 – DATABUF0 Data Buffer DAC0
This bit is set when DATABUF0 register is written.
This bit is cleared when DATABUF0 synchronization is completed.
Value Description
0
No ongoing synchronized access.
1
Synchronized access is ongoing.
Bit 3 – DATA1 Data DAC1
This bit is set when DATA1 register is written.
This bit is cleared when DATA1 synchronization is completed.
Value Description
0
No ongoing synchronized access.
1
Synchronized access is ongoing.
SAM D5x/E5x Family Data Sheet
DAC – Digital-to-Analog Converter
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1697