Datasheet

47.7 Register Summary
Offset Name Bit Pos.
0x00 CTRLA 7:0 ENABLE SWRST
0x01 CTRLB 7:0 REFSEL[1:0] DIFF
0x02 EVCTRL 7:0 RESRDYEO1 RESRDYEO0 INVEI1 INVEI0 EMPTYEO1 EMPTYEO0 STARTEI1 STARTEI0
0x03 Reserved
0x04 INTENCLR 7:0 OVERRUN1 OVERRUN0 RESRDY1 RESRDY0 EMPTY1 EMPTY0 UNDERRUN1 UNDERRUN0
0x05 INTENSET 7:0 OVERRUN1 OVERRUN0 RESRDY1 RESRDY0 EMPTY1 EMPTY0 UNDERRUN1 UNDERRUN0
0x06 INTFLAG 7:0 OVERRUN1 OVERRUN0 RESRDY1 RESRDY0 EMPTY1 EMPTY0 UNDERRUN1 UNDERRUN0
0x07 STATUS 7:0 EOC1 EOC0 READY1 READY0
0x08 SYNCBUSY
7:0 DATABUF1 DATABUF0 DATA1 DATA0 ENABLE SWRST
15:8
23:16
31:24
0x0C DACCTRL0
7:0 DITHER RUNSTDBY FEXT CCTRL[1:0] ENABLE LEFTADJ
15:8 OSR[2:0] REFRESH[3:0]
0x0E DACCTRL1
7:0 DITHER RUNSTDBY FEXT CCTRL[1:0] ENABLE LEFTADJ
15:8 OSR[2:0] REFRESH[3:0]
0x10 DATA0
7:0 DATA[7:0]
15:8 DATA[15:8]
0x12 DATA1
7:0 DATA[7:0]
15:8 DATA[15:8]
0x14 DATABUF0
7:0 DATABUF[7:0]
15:8 DATABUF[15:8]
0x16 DATABUF1
7:0 DATABUF[7:0]
15:8 DATABUF[15:8]
0x18 DBGCTRL 7:0 DBGRUN
0x19
...
0x1B
Reserved
0x1C RESULT0
7:0 RESULT[7:0]
15:8 RESULT[15:8]
0x1E RESULT1
7:0 RESULT[7:0]
15:8 RESULT[15:8]
47.8 Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the
8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be
accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC
write protection is denoted by the "PAC Write-Protection" property in each individual register description.
For details, refer to 47.5.8 Register Access Protection.
SAM D5x/E5x Family Data Sheet
DAC – Digital-to-Analog Converter
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1684