Datasheet

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If DACx conversion is stopped in standby sleep mode, DACx is also disabled to reduce power

consumption. When exiting standby sleep mode, DACx is enabled again, therefore a certain startup time

is required before starting a new conversion.

DAC Controller is compatible with SleepWalking: if RUNSTDBY=1, when an input event (STARTx) is

detected in sleep mode, the DAC Controller will request GCLK_DAC in order to complete the conversion.

47.6.8 Synchronization

Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers

need to be synchronized when written or read.

An exception is the Channel Enable bit in the Peripheral Channel Control registers (PCHCTRLm.CHEN).

When changing this bit, the bit value must be read-back to ensure the synchronization is complete and to

assert glitch free internal operation. Note that changing the bit value under ongoing synchronization will

not generate an error.

The following bits are synchronized when written:

• Software Reset bit in control register (CTRLA.SWRST)

• Enable bit in control register (CTRLA.ENABLE)

The following registers are synchronized when written:

• DAC0 data register (DATA0)

• DAC1 data register (DATA1)

• DAC0 data buffer register (DATABUF0)

• DAC1 data buffer register (DATABUF1)

Required write synchronization is denoted by the "Write-Synchronized" property in the register

description.