Datasheet

register, and disabled by writing a '1' to the corresponding bit in the Interrupt Enable Clear (INTENCLR)
register.
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled.
The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the DAC
Controller is reset. See 47.8.6 INTFLAG for details on how to clear interrupt flags.
All interrupt requests from the peripheral are ORed together on system level to generate one combined
interrupt request to the NVIC. The user must read the INTFLAG register to determine which interrupt
condition is present.
Note that interrupts must be globally enabled for interrupt requests to be generated.
47.6.6 Events
The DAC Controller can generate the following output events:
• Data Buffer 0 Empty (EMPTY0): Generated when the internal data buffer of DAC0 is empty. Refer to
47.6.4 DMA Operation for details.
• Data Buffer 1 Empty (EMPTY1): Generated when the internal data buffer of DAC1 is empty. Refer to
47.6.4 DMA Operation for details.
• Filter 0 Result Ready (RESRDY0): Generated when standalone filter 0 result is ready.
• Filter 1 Result Ready (RESRDY1): Generated when standalone filter 1 result is ready.
Writing a '1' to an Event Output bit in the Event Control Register (EVCTRL.EMPTYEOx) enables the
corresponding output event. Writing a '0' to this bit disables the corresponding output event. Refer to the
Event System chapter for details on configuring the event system.
The DAC Controller can take the following actions on an input event:
• DAC0 Start Conversion (START0): DATABUF0 value is transferred into DATA0 as soon as DAC0 is
ready for the next conversion, and then conversion is started. START0 is considered as
asynchronous to GCLK_DAC, thus it is resynchronized in the DAC Controller. Refer to 47.6.2.4
Digital to Analog Conversion for details.
• DAC1 Start Conversion (START1): DATABUF1 value is transferred into DATA1 as soon as DAC1 is
ready for the next conversion, and then conversion is started. START1 is considered as
asynchronous to GCLK_DAC, thus it is resynchronized in the DAC Controller. Refer to 47.6.2.4
Digital to Analog Conversion for details.
Writing a '1' to an Event Input bit in the Event Control register (EVCTRL.STARTEIx) enables the
corresponding action on input event. Writing a '0' to this bit will disable the corresponding action on input
event.
Note: When several events are connected to the DAC Controller, the enabled action will be taken on
any of the incoming events.
By default, DAC Controller detects rising edge events. Falling edge detection can be enabled by writing
'1' to EVCTRL.INVEIx.
Note that if an event occurs before startup time is completed, DATAx is loaded but start of conversion is
ignored.
47.6.7 Sleep Mode Operation
If the Run In Standby bit in the DAC Control x register DACCCTRLx.RUNSTDBY=1, the DACx will
continue the conversions in standby sleep mode.
If DACCCTRLx.RUNSTDBY=0, the DACx will stop conversions in standby sleep mode.
SAM D5x/E5x Family Data Sheet
DAC – Digital-to-Analog Converter
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1678