Datasheet

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Table Of Contents

• The frequency of GCLK_DAC must be equal or lower than 12MHz (corresponding to 1MSPS).

47.6.4 DMA Operation

In single mode (CTRLB.DIFF=0), DAC Controller generates the following DMA requests:

• Data Buffer 0 Empty (EMPTY0): The request is set when data is transferred from DATABUF0 or

DATA0 to the internal data buffer of DAC0. The request is cleared when either DATA0 register or

DATABUF0 register is written, or by writing a '1' to the EMPTY0 bit in the Interrupt Flag register

(INTFLAG.EMPTY0).

• Data Buffer 1 Empty (EMPTY1): The request is set when data is transferred from DATABUF1 or

DATA1 to the internal data buffer of DAC1. The request is cleared when either DATA0 register or

DATABUF1 register is written, or by writing a one to the EMPTY1 bit in the Interrupt Flag register

(INTFLAG.EMPTY1).

• Filter 0 Result Ready (RESRDY0): The request is set when the filter is used as standalone, and filter

output is ready. The request is cleared by writing a '1' to the RESRDY0 bit in the Interrupt Flag

• Filter 1 Result Ready (RESRDY1): The request is set when the filter is used as standalone, and filter

output is ready. The request is cleared by writing a '1' to the RESRDY1 bit in the Interrupt Flag

In differential mode (CTRLB.DIFF=1), DAC Controller generates the following DMA request:

• Data Buffer 0 Empty (EMPTY0): The request is set when data is transferred from DATABUF0 or

DATA0 to the internal data buffer of DAC1. The request is cleared when either DATA0 register or

DATABUF0 register is written, or by writing a one to the EMPTY0 bit in the Interrupt Flag register

(INTFLAG.EMPTY0).

If the CPU accesses the registers which are source of DMA request set/clear condition, the DMA request

can be lost or the DMA transfer can be corrupted, if enabled.

47.6.5 Interrupts

The DAC Controller has the following interrupt sources:

• DAC0 Data Buffer Empty (EMPTY0): Indicates that the internal data buffer of DAC0 is empty.

• DAC1 Data Buffer Empty (EMPTY1): Indicates that the internal data buffer of DAC1 is empty.

• DAC0 Underrun (UNDERRUN0): Indicates that the internal data buffer of DAC0 is empty and a

DAC0 start of conversion event occurred. Refer to 47.5.6 Events for details.

• DAC1 Underrun (UNDERRUN1): Indicates that the internal data buffer of DAC1 is empty and a

DAC1 start of conversion event occurred. Refer to 47.5.6 Events for details.

• Filter 0 Result Ready (RESRDY0): Indicates that Filter 0 result is ready if set as standalone filter.

• Filter 1 Result Ready (RESRDY1): Indicates that Filter 1 result is ready if set as standalone filter.

• Filter 0 Overrun (OVERRUN0): Indicates that the DMA request has not been cleared while the

RESULT0 register gets new data.

• Filter 1 Overrun (OVERRUN1): Indicates that the DMA request has not been cleared while the

RESULT1 register gets new data.

These interrupts are asynchronous wake-up sources.

Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status

and Clear (INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be

individually enabled by writing a '1' to the corresponding bit in the Interrupt Enable Set (INTENSET)

SAM D5x/E5x Family Data Sheet

DAC – Digital-to-Analog Converter

Datasheet

DS60001507E-page 1677