Datasheet

• Select the refresh period with the Refresh Period bit field in DACCCTRLx.REFRESH[3:0]. Writing
any value greater than '1' to the REFRESH bit field will enable and select the refresh mode. Refer to
47.6.9.3 Conversion Refresh for details.
• Select the output buffer current according to data rate (for low power application) with the Current
Control bit field DACCTRLx.CCTRL[1:0]. Refer to 47.6.9.2 Output Buffer Current Control for details.
• Select standalone filter usage by writing to DACCTRLx.FEXT. Writing FEXT=1 selects a standalone
filter, FEXT=0 selects the filter integrated to the DAC. See also 47.6.9.6 Interpolation Mode for
details.
• Select the filter oversampling ratio by writing to DACCTRLx.OSR[2:0]. writing OSR=0 selects no
oversampling; writing any other value will enable interpolation of input data. See also 47.6.9.6
Interpolation Mode for details.
Once the DAC Controller is enabled, DACx requires a startup time before the first conversion can start.
The DACx Startup Ready bit in the Status register (STATUS.READYx) indicates that DACx is ready to
convert a data when STATUS.READYx=1.
Conversions started while STATUS.READYx=0 shall be discarded.
VOUTx is at tri-state level if DACx is not enabled.
47.6.2.4 Digital to Analog Conversion
Each DAC converts a digital value (stored in DATAx register) into an analog voltage. The conversion
range is between GND and the selected DAC voltage reference VREF. The default source for VREF is
the internal reference voltage VREF. Other voltage reference options are the analog supply voltage
(VDDANA) and the external voltage reference (VREFA). The voltage reference is selected by writing to
the Reference Selection bits in the Control B register (CTRLB.REFSEL).
The output voltage from the DAC can be calculated using the following formula:

OUTx
=
DATAx
4095
× VREF
A new conversion starts as soon as a new value is loaded into DATAx. DATAx can either be loaded via
the APB bus during a CPU write operation, using DMA, or from the DATABUFx register when a STARTx
event occurs.
Refer to 47.5.6 Events for details. Even if both DAC use the same GCLK, each data conversion can be
started independently.
The conversion time is given by the period T
GCLK
of the generic clock GCLK_DAC and the number of bits:

CONV
= 12 × 2 × 
GCLK
The End Of Conversion bit in the Status register indicates that a conversion is completed
(STATUS.EOCx=1). This means that VOUTx is stable.
SAM D5x/E5x Family Data Sheet
DAC – Digital-to-Analog Converter
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1675