Datasheet

47.5.9 Analog Connections
The DAC has up to two analog output pins (VOUT0, VOUT1) and one analog input pin (VREFA) that
must be configured first.
When an internal input is used, it must be enabled before DAC Controller is enabled.
The analog signals of AC, ADC, DAC and OPAMP can be interconnected.
See Analog Connections of Peripherals for details.
47.6 Functional Description
47.6.1 Principle of Operation
Each DAC converts the digital value located in the Data register (DATA0 or DATA1) into an analog
voltage on the DAC output (VOUT0 or VOUT1, respectively).
A conversion is started when new data is loaded to the Data register. The resulting voltage is available on
the DAC output after the conversion time. A conversion can also be started by input events from Event
System.
47.6.2 Basic Operation
47.6.2.1 Initialization
The following registers are enable-protected, meaning they can only be written when the DAC Controller
is disabled (CTRLA.ENABLE=0):
• Control B register (CTRLB)
• Event Control register (EVCTRL)
• DAC0 Control (DACCTRL0)
• DAC1 Control (DACCTRL1)
Enable-protection is denoted by the Enable-Protected property in the register description.
47.6.2.2 Enabling, Disabling and Resetting
The DAC Controller is enabled by writing a '1' to the Enable bit in the Control A register
(CTRLA.ENABLE). The DAC Controller is disabled by writing a '0' to CTRLA.ENABLE.
The DAC Controller is reset by writing '1' to the Software Reset bit in the Control A register
(CTRLA.SWRST). All registers in the DAC will be reset to their initial state, and the DAC Controller will be
disabled. Refer to 47.8.1 CTRLA for details.
47.6.2.3 DAC Configuration
Each individual DAC is configured by its respective DAC Control register (DACCTRLx)). These settings
are applied when DAC Controller is enabled and can be changed only when DAC Controller is disabled.
• Enable the selected DAC by writing a '1' to DACCTRLx.ENABLE.
• Select the data alignment with DACCCTRLx.LEFTADJ. Writing a '1' will left-align the data
(DATABUFx/DATAx[31:20]). Writing a '0' to LEFTADJ will right-align the data (DATABUFx/
DATAx[11:0]).
• If operation in standby mode is desired for DACx, write a '1' to the Run in Standby bit in the DAC
Control register (DACCCTRLx.RUNSTDBY). If RUNSTDBY=1, DACx continues normal operation
when system is in standby mode. If RUNSTDBY=0, DACx is halted in standby mode.
• Select dithering mode with DACCCTRLx.DITHER. Writing '1' to DITHER will enable dithering mode,
writing a '0' will disable it. Refer to 47.6.9.5 Dithering Mode for details.
SAM D5x/E5x Family Data Sheet
DAC – Digital-to-Analog Converter
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1674