Datasheet

This generic clock is asynchronous to the bus clock (CLK_DAC_APB). Due to this asynchronicity, writes
to certain registers will require synchronization between the clock domains. Refer to 47.6.8
Synchronization for further details.
Related Links
15.6.2.6 Peripheral Clock Masking
14. GCLK - Generic Clock Controller
47.5.4 DMA
The DMA request line is connected to the DMA Controller (DMAC). Using the DAC Controller DMA
requests requires to configure the DMAC first.
Related Links
22. DMAC – Direct Memory Access Controller
47.5.5 Interrupts
The interrupt request line is connected to the interrupt controller. Using the DAC Controller interrupts
requires the interrupt controller to be configured first.
Related Links
10.2 Nested Vector Interrupt Controller
10.2 Nested Vector Interrupt Controller
47.5.6 Events
The events are connected to the Event System.
Related Links
31. EVSYS – Event System
47.5.7 Debug Operation
When the CPU is halted in debug mode the DAC will halt normal operation. Any on-going conversions will
be completed. The DAC can be forced to continue normal operation during debugging. If the DAC is
configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar,
improper operation or data loss may result during debugging.
Related Links
47.8.15 DBGCTRL
47.5.8 Register Access Protection
All registers with write access can be write-protected optionally by the Peripheral Access Controller
(PAC), except for the following registers:
• Interrupt Flag Status and Clear (INTFLAG) register
• Data Buffer (DATABUFx) registers
Optional write protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write
Protection" property in each individual register description.
PAC write protection does not apply to accesses through an external debugger.
Related Links
27. PAC - Peripheral Access Controller
SAM D5x/E5x Family Data Sheet
DAC – Digital-to-Analog Converter
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1673