Datasheet

46.8.4 Interrupt Enable Clear
Name: INTENCLR
Offset: 0x04
Reset: 0x00
Property: PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
Bit 7 6 5 4 3 2 1 0
WIN0 COMP1 COMP0
Access
R/W R/W R/W
Reset 0 0 0
Bit 4 – WIN0 Window 0 Interrupt Enable
Reading this bit returns the state of the Window 0 interrupt enable.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit disables the Window 0 interrupt.
Value Description
0
The Window 0 interrupt is disabled.
1
The Window 0 interrupt is enabled.
Bits 0, 1 – COMPx Comparator x Interrupt Enable
Reading this bit returns the state of the Comparator x interrupt enable.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit disables the Comparator x interrupt.
Value Description
0
The Comparator x interrupt is disabled.
1
The Comparator x interrupt is enabled.
SAM D5x/E5x Family Data Sheet
AC – Analog Comparators
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1658