Datasheet

When RUNSTDBY is one, any enabled AC interrupt source can wake up the CPU. The AC can also be
used during sleep modes where the clock used by the AC is disabled, provided that the AC is still
powered (not in shutdown). In this case, the behavior is slightly different and depends on the
measurement mode, as listed in Table 46-2.
Table 46-2. Sleep Mode Operation
COMPCTRLx.MODE RUNSTDBY=0 RUNSTDBY=1
0 (Continuous) COMPx disabled GCLK_AC stopped, COMPx enabled
1 (Single-shot) COMPx disabled GCLK_AC stopped, COMPx enabled only when triggered by
an input event
46.6.13.1 Continuous Measurement during Sleep
When a comparator is enabled in continuous measurement mode and GCLK_AC is disabled during
sleep, the comparator will remain continuously enabled and will function asynchronously. The current
state of the comparator is asynchronously monitored for changes. If an edge matching the interrupt
condition is found, GCLK_AC is started to register the interrupt condition and generate events. If the
interrupt is enabled in the Interrupt Enable registers (INTENCLR/SET), the AC can wake up the device;
otherwise GCLK_AC is disabled until the next edge detection. Filtering is not possible with this
configuration.
Figure 46-9. Continuous Mode SleepWalking
GCLK_AC
STATUSB.READYx
Sampled
Comparator Output
COMPCTRLx.ENABLE
t
STARTUP
Write ‘1’
2-3 cycles
46.6.13.2 Single-Shot Measurement during Sleep
For low-power operation, event-triggered measurements can be performed during sleep modes. When
the event occurs, the Power Manager will start GCLK_AC. The comparator is enabled, and after the start-
up time has passed, a comparison is done, with filtering if desired, and the appropriate peripheral events
and interrupts are also generated, as shown in Figure 46-10. The comparator and GCLK_AC are then
disabled again automatically, unless configured to wake the system from sleep. Filtering is allowed with
this configuration.
Figure 46-10. Single-Shot SleepWalking
GCLK_AC
Comparator
Output or Event
Input Event
t
STARTUP
t
STARTUP
46.6.14 Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers
need to be synchronized when written or read.
The following bits are synchronized when written:
• Software Reset bit in Control register (CTRLA.SWRST)
SAM D5x/E5x Family Data Sheet
AC – Analog Comparators
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1651