Datasheet

Value Description
1
The Generator is kept running and output to its dedicated GCLK_IO pin during Standby
mode.
Bit 12 – DIVSEL Divide Selection
This bit determines how the division factor of the clock source of the Generator will be calculated from
DIV. If the clock source should not be divided, DIVSEL must be 0 and the GENCTRLn.DIV value must be
either 0 or 1.
Value Description
0
The Generator clock frequency equals the clock source frequency divided by
GENCTRLn.DIV.
1
The Generator clock frequency equals the clock source frequency divided by 2^(N+1), where
N is the Division Factor Bits for the selected generator (refer to GENCTRLn.DIV).
Bit 11 – OE Output Enable
This bit is used to output the Generator clock output to the corresponding pin (GCLK_IO), as long as
GCLK_IO is not defined as the Generator source in the GENCTRLn.SRC bit field.
Value Description
0
No Generator clock signal on pin GCLK_IO.
1
The Generator clock signal is output on the corresponding GCLK_IO, unless GCLK_IO is
selected as a generator source in the GENCTRLn.SRC bit field.
Bit 10 – OOV Output Off Value
This bit is used to control the clock output value on pin (GCLK_IO) when the Generator is turned off or the
OE bit is zero, as long as GCLK_IO is not defined as the Generator source in the GENCTRLn.SRC bit
field.
Value Description
0
The GCLK_IO will be LOW when generator is turned off or when the OE bit is zero.
1
The GCLK_IO will be HIGH when generator is turned off or when the OE bit is zero.
Bit 9 – IDC Improve Duty Cycle
This bit is used to improve the duty cycle of the Generator output to 50/50 for odd division factors.
Value Description
0
Generator output clock duty cycle is not balanced to 50/50 for odd division factors.
1
Generator output clock duty cycle is 50/50.
Bit 8 – GENEN Generator Enable
This bit is used to enable and disable the Generator.
Value Description
0
Generator is disabled.
1
Generator is enabled.
Bits 4:0 – SRC[4:0] Generator Clock Source Selection
These bits select the Generator clock source, as shown in this table.
Table 14-4. Generator Clock Source Selection
Value Name Description
0x00 XOSC0 XOSC 0 oscillator output
SAM D5x/E5x Family Data Sheet
GCLK - Generic Clock Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 165