Datasheet

Figure 46-5. VDD Scaler
SCALERx.
VALUE
to
COMPx
6
COMPCTRLx.MUXPOS == 4
COMPCTRLx.MUXNEG == 5
OR
46.6.6 Input Hysteresis
Application software can selectively enable/disable hysteresis for the comparison. Applying hysteresis will
help prevent constant toggling of the output, which can be caused by noise when the input signals are
close to each other.
Hysteresis is enabled for each comparator individually by the Hysteresis Enable bit in the Comparator x
Control register (COMPCTRLx.HYSTEN). Furthermore, when enabled, the level of hysteresis is
programmable through the Hysteresis Level bits also in the Comparator x Control register
(COMPCTRLx.HYST). Hysteresis is available only in Continuous mode (COMPCTRLx.SINGLE=0).
46.6.7 Filtering
The output of the comparators can be filtered digitally to reduce noise. The filtering is determined by the
Filter Length bits in the Comparator Control x register (COMPCTRLx.FLEN), and is independent for each
comparator. Filtering is selectable from none, 3-bit majority (N=3) or 5-bit majority (N=5) functions. Any
change in the comparator output is considered valid only if N/2+1 out of the last N samples agree. The
filter sampling rate is the GCLK_AC frequency.
Note that filtering creates an additional delay of N-1 sampling cycles from when a comparison is started
until the comparator output is validated. For Continuous mode, the first valid output will occur when the
required number of filter samples is taken. Subsequent outputs will be generated every cycle based on
the current sample plus the previous N-1 samples, as shown in Figure 46-6. For Single-shot mode, the
comparison completes after the Nth filter sample, as shown in Figure 46-7.
Figure 46-6. Continuous Mode Filtering
Sampling Clock
Sampled
Comparator Output
3-bit Majority
Filter Output
5-bit Majority
Filter Output
SAM D5x/E5x Family Data Sheet
AC – Analog Comparators
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1648