Datasheet

14.8.3 Generator Control
Name: GENCTRLn
Offset: 0x20 + n*0x04 [n=0..11]
Reset: 0x00000106
Property: PAC Write-Protection, Write-Synchronized
GENCTRLn controls the settings of Generic Generator n (n=[11:0]). The reset value is 0x00000106 for
Generator n=0, else 0x00000000
Bit 31 30 29 28 27 26 25 24
DIV[15:8]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
DIV[7:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
RUNSTDBY DIVSEL OE OOV IDC GENEN
Access
Reset 0 0 0 0 0 1
Bit 7 6 5 4 3 2 1 0
SRC[4:0]
Access
R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Bits 31:16 – DIV[15:0] Division Factor
These bits represent a division value for the corresponding Generator. The actual division factor is
dependent on the state of DIVSEL. The number of relevant DIV bits for each Generator can be seen in
this table. Written bits outside of the specified range will be ignored.
Table 14-3. Division Factor Bits
Generic Clock Generator Division Factor Bits Maximum Division Factor
Generator 0 8 division factor bits - DIV[7:0] 512
Generator 1 16 division factor bits - DIV[15:0] 131072
Generator 2 - 11 8 division factor bits - DIV[7:0] 512
Bit 13 – RUNSTDBY Run in Standby
This bit is used to keep the Generator running in Standby as long as it is configured to output to a
dedicated GCLK_IO pin. If GENCTRLn.OE is zero, this bit has no effect and the generator will only be
running if a peripheral requires the clock.
Value Description
0
The Generator is stopped in Standby and the GCLK_IO pin state (one or zero) will be
dependent on the setting in GENCTRL.OOV.
SAM D5x/E5x Family Data Sheet
GCLK - Generic Clock Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 164