Datasheet

45.8.21 DSEQSTAT
Name: DSEQSTAT
Offset: 0x3C
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
BUSY
Access
R
Reset 0
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
OFFSETCORR
Access
R
Reset 0
Bit 7 6 5 4 3 2 1 0
GAINCORR WINUT WINLT SAMPCTRL AVGCTRL REFCTRL CTRLB INPUTCTRL
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 31 – BUSY DMA Sequencing Busy
The bit is set when the DMA sequencing is enabled or restarted.
The bit is cleared when the DMA sequencing is disabled.
Bit 8 – OFFSETCORR Offset Correction
Value Description
0
DMA update of the Offset Correction register is complete or disabled.
1
DMA update of the Offset Correction register is enabled.
Bit 7 – GAINCORR Gain Correction
Value Description
0
DMA update of the Gain Correction register is complete or disabled.
1
DMA update of the Gain Correction register is enabled.
Bit 6 – WINUT Window Monitor Upper Threshold
Value Description
0
DMA update of the Window Monitor Upper Threshold register is complete or disabled.
1
DMA update of the Window Monitor Upper Threshold register is enabled.
Bit 5 – WINLT Window Monitor Lower Threshold
Value Description
0
DMA update of the Window Monitor Lower Threshold register is complete or disabled.
SAM D5x/E5x Family Data Sheet
ADC – Analog-to-Digital Converter
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1635