Datasheet

45.8.18 Synchronization Busy
Name: SYNCBUSY
Offset: 0x30
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
RBSSW
Access
R
Reset 0
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
SWTRIG OFFSETCORR GAINCORR WINUT
Access
R R R R
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
WINLT SAMPCTRL AVGCTRL REFCTRL CTRLB INPUTCTRL ENABLE SWRST
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 31 – RBSSW Reset BootStrap Switch Synchronization Busy
Bit 11 – SWTRIG Software Trigger Synchronization Busy
This bit is cleared when the synchronization of SWTRIG register between the clock domains is complete.
This bit is set when the synchronization of SWTRIG register between clock domains is started.
Note: For the slave ADC, this bit is always read zero when the SLAVEEN bit is set (CTRLA.SLAVEEN=
1).
Bit 10 – OFFSETCORR Offset Correction Synchronization Busy
This bit is cleared when the synchronization of OFFSETCORR register between the clock domains is
complete.
This bit is set when the synchronization of OFFSETCORR register between clock domains is started.
Bit 9 – GAINCORR Gain Correction Synchronization Busy
This bit is cleared when the synchronization of GAINCORR register between the clock domains is
complete.
This bit is set when the synchronization of GAINCORR register between clock domains is started.
Bit 8 – WINUT Window Monitor Upper Threshold Synchronization Busy
This bit is cleared when the synchronization of WINUT register between the clock domains is complete.
This bit is set when the synchronization of WINUT register between clock domains is started.
SAM D5x/E5x Family Data Sheet
ADC – Analog-to-Digital Converter
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1630