Datasheet

Table Of Contents
14.8.2 Synchronization Busy
Name:  SYNCBUSY
Offset:  0x04
Reset:  0x00000000
Property: 
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
GENCTRL[11:6]
Access
R R R R R R
Reset 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
GENCTRL[5:0] SWRST
Access
R R R R R R R
Reset 0 0 0 0 0 0 0
Bits 13:2 – GENCTRL[11:0] Generator Control n Synchronization Busy
This bit is cleared when the synchronization of the Generator Control n register (GENCTRLn) between
clock domains is complete, or when clock switching operation is complete.
This bit is set when the synchronization of the Generator Control n register (GENCTRLn) between clock
domains is started.
Bit 0 – SWRST Software Reset Synchronization Busy
This bit is cleared when the synchronization of the CTRLA.SWRST register bit between clock domains is
complete.
This bit is set when the synchronization of the CTRLA.SWRST register bit between clock domains is
started.
SAM D5x/E5x Family Data Sheet
GCLK - Generic Clock Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 163