Datasheet

Table Of Contents

45.8.16 Interrupt Flag Status and Clear

Name: INTFLAG

Offset: 0x2E

Reset: 0x00

Property: –

Bit 7 6 5 4 3 2 1 0

WINMON OVERRUN RESRDY

Access

R/W R/W R/W

Reset 0 0 0

Bit 2 – WINMON Window Monitor Interrupt Flag

This flag is cleared by writing a '1' to the flag or by reading the RESULT register.

This flag is set on the next GCLK_ADC cycle after a match with the window monitor condition, and an

interrupt request will be generated if INTENCLR/SET.WINMON is '1'.

Writing a '0' to this bit has no effect.

Writing a '1' to this bit clears the Window Monitor interrupt flag.

Bit 1 – OVERRUN Overrun Interrupt Flag

This flag is cleared by writing a '1' to the flag.

This flag is set if RESULT is written before the previous value has been read by CPU, and an interrupt

request will be generated if INTENCLR/SET.OVERRUN=1.

Writing a '0' to this bit has no effect.

Writing a '1' to this bit clears the Overrun interrupt flag.

Bit 0 – RESRDY Result Ready Interrupt Flag

This flag is cleared by writing a '1' to the flag or by reading the RESULT register.

This flag is set when the conversion result is available, and an interrupt will be generated if INTENCLR/

SET.RESRDY=1.

Writing a '0' to this bit has no effect.

Writing a '1' to this bit clears the Result Ready interrupt flag.

SAM D5x/E5x Family Data Sheet

ADC – Analog-to-Digital Converter

Datasheet

DS60001507E-page 1628