Datasheet

45.8.14 Interrupt Enable Clear
Name: INTENCLR
Offset: 0x2C
Reset: 0x00
Property: PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Bit 7 6 5 4 3 2 1 0
WINMON OVERRUN RESRDY
Access
R/W R/W R/W
Reset 0 0 0
Bit 2 – WINMON Window Monitor Interrupt Disable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Window Monitor Interrupt Enable bit, which disables the corresponding
interrupt request.
Value Description
0
The window monitor interrupt is disabled.
1
The window monitor interrupt is enabled, and an interrupt request will be generated when the
Window Monitor interrupt flag is set.
Bit 1 – OVERRUN Overrun Interrupt Disable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Overrun Interrupt Enable bit, which disables the corresponding
interrupt request.
Value Description
0
The Overrun interrupt is disabled.
1
The Overrun interrupt is enabled, and an interrupt request will be generated when the
Overrun interrupt flag is set.
Bit 0 – RESRDY Result Ready Interrupt Disable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Result Ready Interrupt Enable bit, which disables the corresponding
interrupt request.
Value Description
0
The Result Ready interrupt is disabled.
1
The Result Ready interrupt is enabled, and an interrupt request will be generated when the
Result Ready interrupt flag is set.
SAM D5x/E5x Family Data Sheet
ADC – Analog-to-Digital Converter
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1626