Datasheet

45.8.5 Control B
Name: CTRLB
Offset: 0x06
Reset: 0x0000
Property: PAC Write-Protection, Write-Synchronized
Bit 15 14 13 12 11 10 9 8
WINSS WINMODE[2:0]
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
RESSEL[1:0] CORREN FREERUN LEFTADJ
Access
R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Bit 11 – WINSS Window Single Sample
When this bit is written the window functionality is working on each conversions and not on the
accumulated value. The number of convesions matching with the window comparator is available on
STATUS register (STATUS.WCC). The last sample result is available on RESS register.
Bits 10:8 – WINMODE[2:0] Window Monitor Mode
These bits enable and define the window monitor mode.
Value Name Description
0x0
DISABLE No window mode (default)
0x1
MODE1 RESULT > WINLT
0x2
MODE2 RESULT < WINUT
0x3
MODE3 WINLT < RESULT < WINUT
0x4
MODE4 !(WINLT < RESULT < WINUT)
0x5 -
0x7
Reserved
Bits 4:3 – RESSEL[1:0] Conversion Result Resolution
These bits define whether the ADC completes the conversion 12-, 10- or 8-bit result resolution.
Value Name Description
0x0
12BIT 12-bit result
0x1
16BIT For averaging mode output
0x2
10BIT 10-bit result
0x3
8BIT 8-bit result
Bit 2 – CORREN Digital Correction Logic Enable
The ADC conversion result in the RESULT register is then corrected for gain and offset based on the
values in the GAINCORR and OFFSETCORR registers. Conversion time will be increased by 13 cycles
according to the value in the Offset Correction Value bit group in the Offset Correction register.
Value Description
0
Disable the digital result correction
1
Enable the digital result correction
SAM D5x/E5x Family Data Sheet
ADC – Analog-to-Digital Converter
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1616