Datasheet

The ADC can take the following actions on an input event:
• Start conversion (START): Start a conversion. Refer to SWTRIG register for details.
• Conversion flush (FLUSH): Flush the conversion. Refer to SWTRIG register for details.
Setting an Event Input bit in the Event Control register (EVCTRL.xxEI=1) enables the corresponding
action on input event. Clearing this bit disables the corresponding action on input event.
The ADC uses only asynchronous events, so the asynchronous Event System channel path must be
configured. By default, the ADC will detect a rising edge on the incoming event. If the ADC action must be
performed on the falling edge of the incoming event, the event line must be inverted first. This is done by
setting the corresponding Event Invert Enable bit in Event Control register (EVCTRL.xINV=1).
Note: If several events are connected to the ADC, the enabled action will be taken on any of the
incoming events. If FLUSH and START events are available at the same time, the FLUSH event has
priority.
Related Links
45.8.2 EVCTRL
45.8.5 CTRLB
45.8.13 SWTRIG
31. EVSYS – Event System
45.6.7 Sleep Mode Operation
The ONDEMAND and RUNSTDBY bits in the Control A register (CTRLA) control the behavior of the ADC
during standby sleep mode, in cases where the ADC is enabled (CTRLA.ENABLE = 1). For further details
on available options, refer to Table 45-6.
Note: When CTRLA.ONDEMAND=1, the analog block is powered-off when the conversion is complete.
When a start request is detected, the system returns from sleep and starts a new conversion after the
start-up time delay.
Table 45-6. ADC Sleep Behavior
CTRLA.RUNSTDBY CTRLA.ONDEMAND CTRLA.ENABLE Description
x x 0 Disabled
0 0 1 Run in all sleep modes except
STANDBY.
0 1 1 Run in all sleep modes on request,
except STANDBY.
1 0 1 Run in all sleep modes.
1 1 1 Run in all sleep modes on request.
45.6.8 Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers
need to be synchronized when written or read.
The following bits are synchronized when written:
• Software Reset bit in Control A register (CTRLA.SWRST)
• Enable bit in Control A register (CTRLA.ENABLE)
SAM D5x/E5x Family Data Sheet
ADC – Analog-to-Digital Converter
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1604