Datasheet

• Reset and reconfigure master ADC (ADC0.CTRLA.SWRST = 1)
• Enable the flush event (EVCTRL.FLUSHEI = 1)
Start Trigger
(Software or Event)
ADC0 Start Conversion
ADC0 Start Conversion ADC0 Start Conversion
ADC1 Start Conversion
ADC1 Start Conversion
45.6.4 DMA Operation
The ADC generates the following DMA request:
• Result Conversion Ready (RESRDY): the request is set when a conversion result is available and
cleared when the RESULT register is read. When the averaging operation is enabled, the DMA
request is set when the averaging is completed and result is available.
• DMA Sequencing (DSEQ): for details refer to "add link to DMA sequencing"
45.6.5 Interrupts
The ADC has the following interrupt sources:
• Result Conversion Ready: RESRDY
• Window Monitor: WINMON
• Overrun: OVERRUN
These interrupts, except the OVERRUN interrupt, are asynchronous wake-up sources. See Sleep Mode
Controller for details.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status
and Clear (INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be
individually enabled by writing a one to the corresponding bit in the Interrupt Enable Set (INTENSET)
register, and disabled by writing a one to the corresponding bit in the Interrupt Enable Clear (INTENCLR)
register. An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is
enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or
the ADC is reset. See INTFLAG register for details on how to clear interrupt flags. All interrupt requests
from the peripheral are ORed together on system level to generate one combined interrupt request to the
NVIC. Refer to Nested Vector Interrupt Controller for details. The user must read the INTFLAG register to
determine which interrupt condition is present.
Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to Nested
Vector Interrupt Controller for details.
Related Links
45.8.16 INTFLAG
45.6.6 Events
The ADC can generate the following output events:
• Result Ready (RESRDY): Generated when the conversion is complete and the result is available.
Refer to EVCTRL register for details.
• Window Monitor (WINMON): Generated when the window monitor condition match. Refer to CTRLB
register for details.
Setting an Event Output bit in the Event Control Register (EVCTRL.xxEO=1) enables the corresponding
output event. Clearing this bit disables the corresponding output event. Refer to the Event System
chapter for details on configuring the event system.
SAM D5x/E5x Family Data Sheet
ADC – Analog-to-Digital Converter
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1603