Datasheet

14.7 Register Summary
Offset Name Bit Pos.
0x00 CTRLA 7:0 SWRST
0x01
...
0x03
Reserved
0x04 SYNCBUSY
7:0 GENCTRL[5:0] SWRST
15:8 GENCTRL[11:6]
23:16
31:24
0x08
...
0x1F
Reserved
0x20 GENCTRL0
7:0 SRC[4:0]
15:8 RUNSTDBY DIVSEL OE OOV IDC GENEN
23:16 DIV[7:0]
31:24 DIV[15:8]
...
0x4C GENCTRL11
7:0 SRC[4:0]
15:8 RUNSTDBY DIVSEL OE OOV IDC GENEN
23:16 DIV[7:0]
31:24 DIV[15:8]
0x50
...
0x7F
Reserved
0x80 PCHCTRL0
7:0 WRTLOCK CHEN GEN[3:0]
15:8
23:16
31:24
...
0x013C PCHCTRL47
7:0 WRTLOCK CHEN GEN[3:0]
15:8
23:16
31:24
14.8 Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the
8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be
accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC
write protection is denoted by the "PAC Write-Protection" property in each individual register description.
For details, refer to 14.5.8 Register Access Protection.
SAM D5x/E5x Family Data Sheet
GCLK - Generic Clock Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 160