Datasheet

Table 45-5. DSEQ Trigger Generation and Internal ADC Register updates
Condition Value Action when DMA writes to DSEQDATA
DSEQSTAT.INPUTCT
RL or
DSEQSTAT.CTRLB
0 • No DMA trigger is generated
• No data in the memory must be reserved
1 • A DMA trigger is generated
• One word (32-bit) must be reserved in the memory
• INPUTCTRL ← DSEQDATA[15:0] if
DSEQSTAT.INPUTCTRL = 1
• CTRLB ← DSEQDATA[31:16] if DSEQSTAT.CTRLB = 1
DSEQSTAT.REFCTRL
or
DSEQSTAT.AVGCTRL
or
DSEQSTAT.SAMPCT
RL
0 • No DMA trigger is generated
• No data in the memory must be reserved
1 • A DMA trigger is generated
• One word (32-bit) must be reserved in the memory
• REFCTRL ← DSEQDATA[7:0] if DSEQSTAT.REFCTRL
= 1
• AVGCTRL ← DSEQDATA[23:16] if
DSEQSTAT.AVGCTRL = 1
• SAMPCTRL ← DSEQDATA[31:24] if
DSEQSTAT.SAMPCTRL = 1
DSEQSTAT.WINLT or
DSEQSTAT.WINUT
0 • No DMA trigger is generated
• No data in the memory must be reserved
1 • A DMA trigger is generated
• One word (32-bit) must be reserved in the memory
• WINLT ← DSEQDATA[15:0] if DSEQSTAT.WINLT = 1
• WINUT ← DSEQDATA[31:16] if DSEQSTAT.WINUT = 1
DSEQSTAT.GAINCOR
R or
DSEQSTAT.OFFSETC
ORR
0 • No DMA trigger is generated
• No data in the memory must be reserved
1 • A DMA trigger is generated
• One word (32-bit) must be reserved in the memory
• GAINCORR ← DSEQDATA[15:0] if
DSEQSTAT.GAINCORR = 1
• OFFSETCORR ← DSEQDATA[31:16] if
DSEQSTAT.OFFSETCORR = 1
The DMA Sequential Status register (DSEQSTAT) stores the remaining registers to be updated by the
DMA. During a sequence and when a write access to the DSEQDATA register is detected, the
DSEQSTAT bits which were source of the corresponding DSEQ trigger will be cleared. When all
DSEQSTAT bits are zero (except BUSY bit), the DSEQCTRL register bits (except AUTOSTART) are
copied into the DSEQSTAT register and a new DMA sequence is started when a new ADC conversion
starts.
SAM D5x/E5x Family Data Sheet
ADC – Analog-to-Digital Converter
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1599