Datasheet

• The DMA Sequencing Stop bit in Input Control register is '1' (INPUTCTRL.DSEQSTOP = 1) and the
ongoing DMA sequence is complete. One additional measurement will be done before the ADC is
disabled.
When the DMA sequencing is disable, the BUSY status bit in the DMA Sequential Status register
(DSEQSTAT.BUSY) is cleared and the DMA trigger generation is disabled.
Note that if the DSEQCTRL register is written to a non-zero value, the DSEQSTOP bit in the INPUTCTRL
register will be cleared and the sequencing operation will not be stopped.
Restarting DMA Sequencing
When the DSEQSTOP bit is set (INPUTCTRL.DSEQSTOP = 1) and the sequence is disabled
(DSEQSTAT.BUSY=0), it is possible to restart the sequencing by enabling one of the following conditions:
• Write the DSEQSTOP bit in Input Control register to zero (INPUTCTRL.DSEQSTOP = 0)
• Apply a FLUSH software command (SWTRIG.FLUSH = 1)
• Enable the flush event (EVCTRL.FLUSHEI). The sequence will restart when the flush event is
received
DMA Sequencing Operation
Each ADC register that is part of the DMA sequencing has a separate enable bit in the DSEQCTRL
register to indicate that this field should be part of the DMA sequencing. When an enable bit in
DSEQCTRL is '1', the respective register will be updated when an access to DSEQDATA is decoded.
The DMA Sequencing (DSEQ) trigger request is generated when BUSY status bit is one
(DSEQSTAT.BUSY=1), the ADC is idle or a new conversion starts, and one of the following condition is
true:
• Input Control or Control B bits in DMA Sequential Control register is '1' (DSEQCTRL.INPUTCTRL=1
or DSEQCTRL.CTRLB=1)
• Reference Control, Sampling Time Control or Average Control bits in DMA Sequential Control
register is set (DSEQCTRL.REFCTRL=1, DSEQCTRL.AVGCTRL=1 or DSEQCTRL.SAMPCTRL=1)
• Window Monitor Upper Threshold or Window Monitor Lower Threshold bits in DMA Sequential
Control register is set (DSEQCTRL.WINUT=1 or DSEQCTRL.WINLT=1)
• Offset Correction or Gain Correction bits in DMA Sequential Control register is set
(DSEQCTRL.GAINCORR=1 or DSEQCTRL.OFFSETCORR=1)
Note: When received, the DMA data must be written to DSEQDATA register only, and only 32-bit DMA
access is supported.
If a field is not enabled for DMA update, the corresponding register update will be ignored when
DSEQDATA register is written. The table below shows the DSEQ trigger generation condition and internal
ADC registers refresh when the DSEQDATA register is written by the DMA.
SAM D5x/E5x Family Data Sheet
ADC – Analog-to-Digital Converter
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1598