Datasheet

When one of these registers is written, the data is stored in the corresponding buffer as long as the
current conversion is not impacted, and the corresponding busy status will be set in the Synchronization
Busy register (SYNCBUSY). When a new RESULT is available, data stored in the buffer registers will be
transfered to the ADC and a new conversion can start.
45.6.3.3 DMA Sequencing
The ADC can sequence a series of conversion. When DMA sequencing is enabled, a set of ADC
configuration registers can be automatically refreshed using the DMA controller.
ADC
REFCTRL
OFFSETCORR
GAINCORR
AVGCTRL
DSEQCTRL
SAMPCTRL
WINUT
CTRLB
WINLT
DSEQDATA
INPUTCTRL
DSEQSTAT
Reload Request
DMA
Controller
Peripheral Bus
Enabling DMA Sequencing
DMA Sequencing is enabled when at least one bit in the DMA Sequence Control register (DSEQCTRL) is
'1'.
When this is the case, the BUSY status bit in the DMA Sequential Status register (DSEQSTAT.BUSY) is
set to '1'.
Disabling DMA Sequencing
DMA Sequencing is disabled when at least one of the following conditions is valid:
• The ADC is disabled (CTRLA.ENABLE = 0).
• The ADC is reset (CTRLA.SWRST = 1).
• The DMA Sequence Control register (DSEQCTRL) is written '0' and the ongoing DMA sequence is
completed.
SAM D5x/E5x Family Data Sheet
ADC – Analog-to-Digital Converter
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1597