Datasheet

Figure 45-7. ADC Timing for Free Running in 8-bit Resolution
CLK_ADC
STATE
CONVERT
SAMPLING
6 5 4 3 2 1
LSB
INT
LSB
MSB SAMPLING
6 5 4 3 2 1
LSB
MSB
SAMPLING
MSB
The propagation delay of an ADC measurement is given by:
PropagationDelay =
1 + Resolution

ADC
Example. In order to obtain 1MSPS in 12-bit resolution with a sampling time length of
four CLK_ADC cycles, f
CLK_ADC
must be 1MSPS * (4 + 12) = 16MHz. As the minimal
division factor of the prescaler is 2, GCLK_ADC must be 32MHz.
45.6.2.9 Accumulation
The results of multiple, consecutive conversions can be accumulated. The number of samples to be
accumulated is specified by the Sample Number field in the Average Control register
(AVGCTRL.SAMPLENUM). When accumulating more than 16 samples, the result will be too large to fit
the 16-bit RESULT register size. To avoid overflow, the result is right shifted automatically to fit within the
available register size. The number of automatic right shifts is specified in the table below.
Note: To perform the accumulation of two or more samples, the Conversion Result Resolution field in
the Control B register (CTRLB.RESSEL) must be set.
Table 45-1. Accumulation
Number of
Accumulated
Samples
AVGCTRL.
SAMPLENUM
Number of
Automatic Right
Shifts
Final Result
Precision
Automatic
Division Factor
1 0x0 0 12 bits 0
2 0x1 0 13 bits 0
4 0x2 0 14 bits 0
8 0x3 0 15 bits 0
16 0x4 0 16 bits 0
32 0x5 1 16 bits 2
64 0x6 2 16 bits 4
128 0x7 3 16 bits 8
256 0x8 4 16 bits 16
512 0x9 5 16 bits 32
1024 0xA 6 16 bits 64
Reserved 0xB –0xF 12 bits 0
SAM D5x/E5x Family Data Sheet
ADC – Analog-to-Digital Converter
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1592