Datasheet

Figure 45-3. ADC Timing for One Conversion in 12-bit Resolution
CLK_ADC
STATE
START
SAMPLING
MSB
10
9 8 7 6 5 4 3 2 1
LSB
INT
The sampling time can be increased by using the Sampling Time Length bit group in the Sampling Time
Control register (SAMPCTRL.SAMPLEN). As example, the next figure is showing the timing conversion
with sampling time increased to six CLK_ADC cycles.
Figure 45-4. ADC Timing for One Conversion with Increased Sampling Time, 12-bit
CLK_ADC
STATE
START
MSB
10 9 8 7 6 5 4 3 2 1
LSB
INT
SAMPLING
The ADC provides also offset compensation, see the following figure. The offset compensation is enabled
by the Offset Compensation bit in the Sampling Control register (SAMPCTRL.OFFCOMP).
Note: If offset compensation is used, the sampling time must be set to one cycle of CLK_ADCx.
In free running mode, the sampling rate R
S
is calculated by
R
S
= f
CLK_ADC
/ ( n
SAMPLING
+ n
OFFCOMP
+ n
DATA
)
Here, n
SAMPLING
is the sampling duration in CLK_ADC cycles, n
OFFCOMP
is the offset compensation
duration in clock cycles, and n
DATA
is the bit resolution. f
CLK_ADC
is the ADC clock frequency from the
internal prescaler: f
CLK_ADC
= f
GCLK_ADC
/ 2^(1 + CTRLA.PRESCALER)
Figure 45-5. ADC Timing for One Conversion with Offset Compensation, 12-bit
CLK_ADC
STATE
START
SAMPLING
MSB
10 9 8 7 6 5 4 3 2 1
LSB
INT
Offset Compensation
The impact of resolution on the sampling rate is seen in the next two figures, where free-running sampling
in 12-bit and 8-bit resolution are compared.
Figure 45-6. ADC Timing for Free Running in 12-bit Resolution
CLK_ADC
STATE
CONVERT
SAMPLING
MSB
10 9 8 7 6 5 4 3 2 1
LSB
INT
SAMPLING
MSB
9 810 7 6
LSB
SAM D5x/E5x Family Data Sheet
ADC – Analog-to-Digital Converter
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1591