Datasheet

Table Of Contents

14.6.5.3 Entering Standby Mode

There may occur a delay when the device is put into Standby, until the power is turned off. This delay is

caused by running Clock Generators: if the Run in Standby bit in the Generator Control register

(GENCTRLn.RUNSTDBY) is '0', GCLK must verify that the clock is turned of properly. The duration of this

verification is frequency-dependent.

Related Links

18. PM – Power Manager

14.6.6 Synchronization

Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers

need to be synchronized when written or read.

An exception is the Channel Enable bit in the Peripheral Channel Control registers (PCHCTRLm.CHEN).

When changing this bit, the bit value must be read-back to ensure the synchronization is complete and to

assert glitch free internal operation. Note that changing the bit value under ongoing synchronization will

not generate an error.

The following registers are synchronized when written:

• Generic Clock Generator Control register (GENCTRLn)

• Control A register (CTRLA)

Required write synchronization is denoted by the "Write-Synchronized" property in the register

description.