Datasheet

Table Of Contents

• Control A (CTRLA), except ENABLE and SWRST bits

• Event Control register (EVCTRL)

• Calibration register (CALIB)

Enable-protection is denoted by the "Enable-Protected" property in the register description.

45.6.2.2 Enabling, Disabling, and Resetting

The ADC is enabled by writing a '1' to the Enable bit in the Control A register (CTRLA.ENABLE). The

ADC is disabled by writing CTRLA.ENABLE=0.

The ADC is reset by writing a '1' to the Software Reset bit in the Control A register (CTRLA.SWRST). All

registers in the ADC, except DBGCTRL, will be reset to their initial state, and the ADC will be disabled.

Refer to 45.8.1 CTRLA for details.

45.6.2.3 Operation

In the most basic configuration, the ADC samples values from the configured internal or external sources

(INPUTCTRL register). The rate of the conversion depends on the combination of the GCLK_ADCx

frequency and the clock prescaler.

To convert analog values to digital values, the ADC needs to be initialized first, as described in the

Initialization section. Data conversion can be started either manually by setting the Start bit in the

Software Trigger register (SWTRIG.START=1), or automatically by configuring an automatic trigger to

initiate the conversions. The ADC starts sampling the input only after the start of conversion is triggered.

This means that even after the MUX selection is made, sample and hold (S&H) operation starts only on

the conversion trigger. A free-running mode can be used to continuously convert an input channel. When

using free-running mode the first conversion must be started, while subsequent conversions will start

automatically at the end of previous conversions.

The ADC starts sampling the input only after the start of a conversion is triggered. This means that even

after the MUX selection is made, sample and hold operation starts only on the conversion trigger.

The result of the conversion is stored in the Result register (RESULT) overwriting the result from the

previous conversion.

To avoid data loss, if more than one channel is enabled, the conversion result must be read as soon as it

is available (INTFLAG.RESRDY). Failing to do so will result in an overrun error condition, indicated by the

OVERRUN bit in the Interrupt Flag Status and Clear register (INTFLAG.OVERRUN).

To enable one of the available interrupts sources, the corresponding bit in the Interrupt Enable Set