Datasheet

Note: One signal can be mapped on several pins.
Related Links
6. I/O Multiplexing and Considerations
45.5 Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
45.5.1 I/O Lines
Using the ADC's I/O lines requires the I/O pins to be configured using the port configuration (PORT).
Related Links
32. PORT - I/O Pin Controller
45.5.2 Power Management
The ADC will continue to operate in any Sleep mode where the selected source clock is running. The
ADC’s interrupts, except the OVERRUN interrupt, can be used to wake up the device from Sleep modes,
except the OVERRUN interrupt. Events connected to the event system can trigger other operations in the
system without exiting Sleep modes.
Related Links
18. PM – Power Manager
45.5.3 Clocks
The ADC bus clocks (CLK_APB_ADCx) can be enabled in the Main Clock, which also defines the default
state.
Each ADC requires a generic clock (GCLK_ADCx). This clock must be configured and enabled in the
Generic Clock Controller (GCLK) before using the ADC.
A generic clock is asynchronous to the bus clock. Due to this asynchronicity, writes to certain registers will
require synchronization between the clock domains. Refer to Synchronization for further details.
Related Links
15.6.2.6 Peripheral Clock Masking
14. GCLK - Generic Clock Controller
45.5.4 DMA
The DMA request line is connected to the DMA Controller (DMAC). Using the ADC DMA requests
requires the DMA Controller to be configured first.
Related Links
22. DMAC – Direct Memory Access Controller
45.5.5 Interrupts
The interrupt request line is connected to the interrupt controller. Using the ADC interrupt requires the
interrupt controller to be configured first.
Related Links
10.2 Nested Vector Interrupt Controller
SAM D5x/E5x Family Data Sheet
ADC – Analog-to-Digital Converter
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1587