Datasheet

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There is one exception concerning the Generator 0. As it is used as GCLK_MAIN, it cannot be locked. It

is reset by any Reset and will start up in a known configuration. The software reset (CTRLA.SWRST) can

not unlock the registers.

In case of an external Reset, the Generator source will be disabled. Even if the WRTLOCK bit is written to

'1' the peripheral channels are disabled (PCHCTRLm.CHEN set to '0') until the Generator source is

enabled again. Then, the PCHCTRLm.CHEN are set to '1' again.

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14.8.1 CTRLA

14.6.4 Additional Features

14.6.4.1 Peripheral Clock Enable after Reset

The Generic Clock Controller must be able to provide a generic clock to some specific peripherals after a

Reset. That means that the configuration of the Generators and Peripheral Channels after Reset is

device-dependent.

Refer to GENCTRLn.SRC for details on GENCTRLn reset.

Refer to PCHCTRLm.SRC for details on PCHCTRLm reset.

14.6.5 Sleep Mode Operation

14.6.5.1 SleepWalking

The GCLK module supports the SleepWalking feature.

If the system is in a sleep mode where the Generic Clocks are stopped, a peripheral that needs its clock

in order to execute a process must request it from the Generic Clock Controller.

The Generic Clock Controller receives this request, determines which Generic Clock Generator is

involved and which clock source needs to be awakened. It then wakes up the respective clock source,

enables the Generator and Peripheral Channel stages successively, and delivers the clock to the

peripheral.

The RUNSTDBY bit in the Generator Control register controls clock output to pin during standby sleep

mode. If the bit is cleared, the Generator output is not available on pin. When set, the GCLK can

continuously output the generator output to GCLK_IO. Refer to 14.6.2.9 External Clock for details.