Datasheet

Table Of Contents

44.7 Register Summary

Offset Name Bit Pos.

0x00 CTRLA 7:0 RUNSTDBY ENABLE

0x01

...

0x03

Reserved

0x04 EVCTRL 7:0 DATARDYEO

0x05

...

0x07

Reserved

0x08 INTENCLR 7:0 DATARDY

0x09 INTENSET 7:0 DATARDY

0x0A INTFLAG 7:0 DATARDY

0x0B

...

0x1F

Reserved

0x20 DATA

7:0 DATA[7:0]

15:8 DATA[15:8]

23:16 DATA[23:16]

31:24 DATA[31:24]

44.8 Register Description

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition,

the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be

accessed directly.

Some registers require synchronization when read and/or written. Synchronization is denoted by the

"Read-Synchronized" and/or "Write-Synchronized" property in each individual register description.

Optional write protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write

Protection" property in each individual register description.

Some registers are enable-protected, meaning they can only be written when the module is disabled.

Enable protection is denoted by the "Enable-Protected" property in each individual register description.

Refer to PAC - Peripheral Access Controller and 44.6.6 Synchronizationfor details.