Datasheet

An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled.
The interrupt request remains active until the interrupt flag is cleared, or the interrupt is disabled. See
44.8.5 INTFLAG for details on how to clear interrupt flags.
Note that interrupts must be globally enabled for interrupt requests to be generated.
Related Links
10.2 Nested Vector Interrupt Controller
44.6.4 Events
The TRNG can generate the following output event:
• Data Ready (DATARDY): Generated when a new random number is available in the DATA register.
Writing '1' to the Data Ready Event Output bit in the Event Control Register (EVCTRL.DATARDYEO)
enables the DTARDY event. Writing a '0' to this bit disables the corresponding output event. Refer to
EVSYS – Event System for details on configuring the Event System.
Related Links
31. EVSYS – Event System
44.6.5 Sleep Mode Operation
The Run in Standby bit in Control A register (CTRLA.RUNSTDBY) controls the behavior of the TRNG
during standby sleep mode:
When this bit is '0', the TRNG is disabled during sleep, but maintains its current configuration.
When this bit is '1', the TRNG continues to operate during sleep and any enabled TRNG interrupt source
can wake up the CPU.
44.6.6 Synchronization
Not applicable.
SAM D5x/E5x Family Data Sheet
TRNG – True Random Number Generator
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1577