Datasheet

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Operation Clock Cycles Timing One block
RSA 2048 encryption / signature verification.
No CRT, Fast implementation, W=1 Exponent=3
0.24 MCycles 2 ms
RSA 2048 encryption / signature verification.
No CRT, Fast implementation, W=1 Exponent=0x10001
0.24 MCycles 2 ms
Table 43-116. RSA4096
Operation Clock Cycles Timing One block
RSA 4096 Decryption / signature generation. No CRT, Regular
implementation, W=1
208 MCycles 1.73s
RSA 4096 Decryption / signature generation. With CRT, Regular
implementation, W=3
45.5 MCycles 379 ms
RSA 4096 encryption / signature verification.
No CRT, Fast implementation, W=1 Exponent=3
0.92 MCycles 7.67 ms
RSA 4096 encryption / signature verification.
No CRT, Fast implementation, W=1 Exponent=0x10001
0.92 MCycles 7.67 ms
43.3.8.3.2 Service Timing for Prime Generation
Prime generation uses the PrimeGen service.
Table 43-117. Prime Generation
Operation Clock Cycles Timing One
Block
Regular Generation of two primes, Prime_Length=512 bits,
W=4, Rabin Miller Iterations Number = 3, (average of 200
samples)
Mean = 47.4
MCycles
Mean = 0.40s
Regular Generation of two primes, Prime_Length=512 bits,
W=4, Rabin Miller Iterations Number = 3, (Standard Deviation
for 200 samples)
Std Dev = 30.3
Mcycles
Std Dev = 0.25s
Regular Generation of two primes, Prime_Length=1024 bits,
W=4, Rabin Miller Iterations Number = 3, (average of 200
samples)
Mean = 448
MCycles
Mean = 3.73s
Regular Generation of two primes, Prime_Length=1024 bits,
W=4, Rabin Miller Iterations Number = 3, (Standard Deviation
for 200 samples)
Std Dev = 294
Mcycles
Std Dev = 2.45s
Regular Generation of two primes, Prime_Length=2048 bits,
W=4, Rabin Miller Iterations Number = 3, (average of 200
samples)
Mean = 4.78
GCycles
Mean = 39.8s
SAM D5x/E5x Family Data Sheet
Public Key Cryptography Controller (PUKCC)
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1571