Datasheet

14.5.3 Clocks
The GCLK bus clock (CLK_GCLK_APB) can be enabled and disabled in the Main Clock Controller.
Related Links
15.6.2.6 Peripheral Clock Masking
29. OSC32KCTRL – 32KHz Oscillators Controller
14.5.4 DMA
Not applicable.
14.5.5 Interrupts
Not applicable.
14.5.6 Events
Not applicable.
14.5.7 Debug Operation
When the CPU is halted in debug mode the GCLK continues normal operation. If the GCLK is configured
in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper
operation or data loss may result during debugging.
14.5.8 Register Access Protection
All registers with write access can be optionally write-protected by the Peripheral Access Controller
(PAC).
Note: Optional write protection is indicated by the "PAC Write Protection" property in the register
description.
Write protection does not apply for accesses through an external debugger.
Related Links
27. PAC - Peripheral Access Controller
14.5.9 Analog Connections
Not applicable.
14.6 Functional Description
14.6.1 Principle of Operation
The GCLK module is comprised of twelve Generic Clock Generators (Generators) sourcing up to 64
Peripheral Channels and the Main Clock signal CLK_MAIN.
A clock source selected as input to a Generator can either be used directly, or it can be prescaled in the
Generator. A generator output is used by one or more Peripheral Channels to provide a peripheral
generic clock signal (GCLK_PERIPH) to the peripherals.
14.6.2 Basic Operation
14.6.2.1 Initialization
Before a Generator is enabled, the corresponding clock source should be enabled. The Peripheral clock
must be configured as outlined by the following steps:
SAM D5x/E5x Family Data Sheet
GCLK - Generic Clock Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 154